Examples

This section illustrates the synthesis flow and some of the tasks described above with a few examples.


Note that you may get different results from synthesis depending on the platform and version used. These examples were made with the version Z-2007.03-SP2 running on Linux.

Modular Ripple Carry Adder

The first example is a simple Ripple Carry Adder (RCA). This example illustrates the basic synthesis flow: reading the design, setting constraints, optimizing the design, reporting and analyzing, and saving the design.


RCA Design Structure

This adder has modular structure as illustrated in pictures below. Figure 2 shows the gate-level structure of the Half Adder (HA) module, which is composed of two gates, AND and exclusive OR. This design is described in file ha.vhd.

ha.vhd:
------------------------------------------------------------------------

-- Project: Design Compiler Tutorial
-- Author: Juha Pirttimäki
-- File: ha.vhd
-- Design: Half Adder
-----------------------------------------------------------------------
-- Description:
-- Half adder circuit
------------------------------------------------------------------------
-- File hierarchy:
-- ha.vhd
------------------------------------------------------------------------
-- Date By MODIFIED


-- 2010/1/9 prhtp Original
--------------------------------------------------------------


library ieee;
use ieee.std_logic_1164.all;
entity ha is
port (
a : in std_logic; -- input a
b : in std_logic; -- input b
s : out std_logic; -- sum bit
co : out std_logic -- carry bit
);
end ha;
architecture RTL of ha is
begin -- RTL
s <= a xor b;
co <= a and b;
end RTL;

The Full Adder (FA) module is composed of two instances of Half Adders and single OR gate as shown in Figure 3. This design is described in file fa.vhd.

------------------------------------------------------------------------

-- Project: Design Compiler Tutorial
-- Author: Juha Pirttimäki
-- File: fa.vhd
-- Design: Full Adder
------------------------------------------------------------------------
-- Description:
-- Full adder circuit. This full adder instantiates two half adders (HA)
-- and a single OR gate.
------------------------------------------------------------------------
-- File hierarchy:
-- fa.vhd
-- + ha.vhd
------------------------------------------------------------------------
-- Date By MODIFIED
-- 2010/1/9 prthpns Original
------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity fa is
port (
a : in std_logic; -- input bit a
b : in std_logic; -- input bit b
ci : in std_logic; -- carry in bit
s : out std_logic; -- sum bit
co : out std_logic -- carry out bit
);
end fa;
architecture RTL of fa is
-- Component and signal declarations
-- Half Adder
component ha
port (
a : in std_logic; -- input bit a
b : in std_logic; -- input bit b
s : out std_logic; -- sum bit
co : out std_logic -- carry out
);
end component;
-- Intermediate signals s_i, c1_i, c2_i
signal s_i : std_logic; -- interm. signal for ha_1 sum
signal c1_i : std_logic; -- interm. signal for ha_1 carry
signal c2_i : std_logic; -- interm. signal for ha_2 carry
begin -- RTL
i_ha_0: ha
port map (
a => a,
b => b,
s => s_i,
co => c1_i
);
i_ha_1: ha
port map (
a => ci,
b => s_i,
s => s,
co => c2_i
);
co <= c1_i or c2_i;
end RTL;

The last part of the design instantiates the RCA design using bus width of 4 bits. The design also registers the output of the adder as shown in Figure 5. The carry in (CI) bit of the RCA is connected low (0) and the carry out (CI) bit is the most significant bit (MSB) of the output bus. This design is described in file adder.vhd.

adder.vhd

------------------------------------------------------------------------


-- Project: Design Compiler Tutorial

-- Author: Juha Pirttimäki

-- File: adder.vhd

-- Design: Generic Adder

------------------------------------------------------------------------

-- Description:

-- Generic adder circuit. This adder is an N bit instantation of the

-- RCA adder. The output of the circuit is registered.

-- NOTE: The carry in bit of the ripple carry adder is tied low. The

-- carry out bit is the Most Significant Bit (MSB; Nth bit) of the

-- output bus 's'.

------------------------------------------------------------------------

-- File hierarchy:

-- adder.vhd

-- + rca.vhd

-- + fa.vhd

-- + ha.vhd

------------------------------------------------------------------------

-- Date By MODIFIED

-- 2007/10/18 JP Original

------------------------------------------------------------------------



library ieee;

use ieee.std_logic_1164.all;



entity adder is



generic (

N : integer := 8 -- Bus width

);



port (

-- Global signals

rst_n : in std_logic; -- System reset

clk : in std_logic; -- System clock



-- I/O signals

a : in std_logic_vector(N-1 downto 0); -- input a

b : in std_logic_vector(N-1 downto 0); -- input b

s : out std_logic_vector(N downto 0) -- sum a+b

);



end adder;



architecture RTL of adder is



-- Component and Signal Declarations

component rca

generic (

N : integer -- Bus width

);

port (

a : in std_logic_vector(N-1 downto 0); -- input a

b : in std_logic_vector(N-1 downto 0); -- input b

ci : in std_logic; -- carry in

s : out std_logic_vector(N-1 downto 0); -- sum out

co : out std_logic -- carry out

);

end component;



-- Intermediate signal s_i

signal s_i : std_logic_vector(N downto 0);



begin -- RTL



i_rca: rca

generic map (

N => N

)

port map (

a => a,

b => b,

ci => '0',

s => s_i(N-1 downto 0),

co => s_i(N)

);



----------------------------------------------------------------------

-- purpose: Output s Registers

-- type : sequential

-- inputs : clk, rst_n

-- outputs: s

----------------------------------------------------------------------

outregs: process (clk, rst_n)

begin -- process outregs

if (rst_n = '0') then -- asynchronous reset (active low)

s <= (others => '0');

elsif (clk'event and clk = '1') then -- rising clock edge

s <= s_i;

end if;

end process outregs;



end RTL;



This example uses the directory structure described earlier in section Directory Structure. Create a directory structure as described and copy the following files (SRC/ha.vhd, SRC/fa.vhd, SRC/rca.vhd, SRC/adder.vhd) into the directory SRC/. Copy also the .synopsys_dc.setup file into your project root directory.







Initialize Design Compiler as shown in section Initialization and invoke the Design Compiler GUI:

$ design_vision

Note that there is no ampersand (&) at the end of the command. In a moment, you should see a screen similar to the one below:

 The Hierarchy Browser displays information about the design in textual form. The Hierarchy Browser is divided into two panes: instance tree (left) and objects list (right). The instance tree displays the design's hierarchy and the objects list information about the objects in current instance.



The Console views display information between the designer and the synthesis tool (commands entered by the designer and messages resulting the commands). Commands can be entered in Console Command Line (or from menubar menus and toolbar buttons).


Note that only some of the most common commands can be entered by using the Design Compiler GUI menubars and buttons. All commands can always be executed by writing them into the console. Therefore, in this tutorial we will mostly write the commands into the console. At the end of the synthesis, we will create a synthesis script file from commands that were executed during this example. This synthesis script file can then be used in subsequent synthesis runs.

Before proceeding with the example you need check that the tool has been set up correctly (i.e. the .synopsys_dc.setup file was read at the start up and there wasn't any problems with that). Our setup file merely sets the libraries that are required for synthesis and defines a library for work files.


Check libraries by selecting File -> Setup... from the menubar. This will open an Application Setup dialog box. In Application Setup check the values for target_library, link_library, symbol_library, and synthetic_library. They should be the same as in the setup file. The search_path should contain ./SRC, ./SYN/SCR, and ${L180_GII} directories in addition to default search path directories.


If the values for libraries or search path is something else then there was a problem with the setup file. In particular, if the values for libraries are your_library.db, your setup file was not read at all. In that case, the most probable reason is that the Design Vision was invoked in a wrong directory (Design Compiler/Vision searches for the setup file from the same directory it is invoked).


Check also that the design library is mapped correctly by writing the following command to the Console Command Line:






get_design_lib_path WORK






This should print the full path to the ./SYN/WORK/ library.

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