Introduction

RTL synthesis is an automated design task in which high-level design descriptions written in Hardware Description Languages (such as VHDL, Verilog, or SystemVerilog) are transformed into gate-level netlists. Gate-level netlist is basically a circuit implementation of the design made of library components (both combinational and sequential cells) available in the technology library and their interconnections. The netlist is generated by the synthesis tool according to the constraints set by the designer. Figure 1 below shows an overview of the synthesis.

Design Compiler is RTL Synthesis tool by Synopsys. It supports UNIX platforms and is installed on Institute's computer systems (see here for available versions on each platform: mustatikli/ linux). Design Compiler is not supported on Windows platform.

This tutorial is intended for users with no previous experience with Design Compiler. It introduces you how to set up the synthesis tool and the basic tasks of logic synthesis with Design Compiler: analyzing and elaborating the design, setting constraints, optimizing the design, analyzing the results, and saving generated netlists. Specifically, this tutorial considers only synchronous systems and basic synthesis tasks. Subjects as asynchronous systems or advanced synthesis techniques will not be discussed. In addition to Design Compiler, this tutorial introduces the basics of the Design Compiler GUI (called Design Vision).

This tutorial includes several examples written in VHDL but, excluding a few commands using VHDL specific command options, all information shown here can also be applied with designs written in Verilog or SystemVerilog. This tutorial was made by using Design Compiler version 2007.03 SP2 on Linux.

Note: the Y Foundation (i.e. versions starting from version 2007.03) introduced some important changes in Synopsys Desing Compiler tool:

The tool supports only XG mode. Support for DB mode has been removed from the tool.

The tool supports only DCTCL command language. Support for DCSH command language has been removed from the tool.

Therefore, this tutorial and its examples consider only Design Compiler running in XG mode using DCTCL command language even though older tools are still available and installed on Institute's computer systems.